View CDC3231G-C_286306.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MICRONAS
CDC 3231G-C Automotive Controller
Edition May 3, 2005 6251-609-1DS
MICRONAS
CDC 3231G-C
Contents Page 3 3 6 7 9 9 10 10 11 13 13 14 15 17 19 21 23 23 25 27 27 29 29 34 35 37 38 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.3. 2.4. 3. 3.1. 3.2. 3.3. 3.4. 4. 5. 6. 6.1. 7. 8. 8.1. 9. 9.1. 9.2. 9.3. 10. 11. Title Introduction Features Abbreviations Block Diagram Packages and Pins Package Outline Dimensions Pin Assignment Pin Function Description External Components Electrical Data Absolute Maximum Ratings Recommended Operating Conditions Characteristics Recommended Quartz Crystal Characteristics CPU and Clock System Memory and Special Function ROM (SFR) System Core Logic Control Word (CW) IRQ Interrupt Controller Unit (ICU) Hardware Options Functional Description Register Cross Reference Table 8-Bit I/O Region 32-Bit I/O Region Modified Registers Differences Data Sheet History
DATA SHEET
2
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
1. Introduction
Release Note: Revision bars changes to the previous edition. indicate significant interfaces and PWM outputs and a crystal clock multiplying PLL. This document provides ROM hardware specific information. General information on operating the IC can be found in the document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251579-1DS).
The device is a microcontroller for use in automotive applications. The on-chip CPU is an ARM processor ARM7TDMI with 32-bit data and address bus, which supports Thumb format instructions. The chip contains timer/counters, interrupt controller, multi channel AD converter, stepper motor and LCD driver, CAN
1.1. Features
Table 1-1: CDC32xxG-C Family Feature List This Device: Item CDC3205GC EMU CDC3207GC MCM Flash CDC3217GC MCM Flash CDC3257GC2 MCM Flash CDC3272GC Mask ROM CDC3231GC Mask ROM
Core CPU CPU-active operation modes Power-saving operation modes (CPU inactive) CPU clock multiplication EMI reduction mode Oscillators RAM, zero wait state, 32 bit wide ROM 32-bit ARM7TDMI DEEP SLOW, SLOW, FAST and PLL IDLE, WAKE and STANDBY PLL delivering up to 50 MHz selectable in PLL mode 4 to 5 MHz quartz and 32 kHz internal RC 32 Kbyte ROMless, ext. up to 4 M x 32/ 8 M x 16 512-Kbyte Flash (256 K x 16) top-boot conf. 1024-Kbyte Flash (512 K x 16) top-boot conf. 12 Kbyte 256-Kbyte Flash (128 K x 16) top-boot conf. 16 Kbyte 384 Kbyte (96 K x 32/ 192 K x 16) 6 Kbyte 128 Kbyte (32 K x 32/ 64 K x 16)
Boot ROM Digital watchdog Central clock divider Interrupt controller expanding IRQ Port interrupts including slope selection Port wake-up inputs including slope/level selection
8 Kbyte (special function ROM) 40 inputs, 16 priority levels 26 inputs, 16 priority levels 5 inputs
6 inputs 10 inputs
Micronas
May 3, 2005; 6251-609-1DS
3
CDC 3231G-C
Table 1-1: CDC32xxG-C Family Feature List
DATA SHEET
This Device: Item CDC3205GC EMU CDC3207GC MCM Flash CDC3217GC MCM Flash CDC3257GC2 MCM Flash CDC3272GC Mask ROM CDC3231GC Mask ROM
Patch module Boot system Device lock module Analog Reset/Alarm Clock and supply supervision 10-bit ADC, charge balance type ADC reference Comparators LCD Communication DMA UART Synchronous serial peripheral interfaces Full CAN modules V2.0B each with a 32-object RAM (LCAN000E) DIGITbus I2C Graphics bus interface Input & Output Universal ports selectable as 4:1-mux LCD segment/backplane lines or digital I/O ports
10 ROM locations allows in-system downloading of external code to Flash memory via JTAG inhibits access to internal firmware, lock can be set by customer -
combined input for regulator input supervision 16 channels (each selectable as digital input) VREF pin, P1.0 pin, P1.1 pin or VREFINT internal bandgap selectable P06COMP with 1/2 AVDD reference, WAITCOMP with internal bandgap reference internal processing of all analog voltages for the LCD driver
3 DMA channels, one each for serving the graphics bus interface, SPI0 and SPI1 2: UART0 and UART1 2: SPI0 and SPI1, DMA supported 4: CAN0, CAN1, CAN2 and CAN3 2: CAN0 and CAN1
UART0
1: CAN0
1 master module 2 master modules: I2C0 and I2C1 8-bit data bus, DMA supported, e.g., for connection of EPSON SED 1560 LCD controller
I2C0 -
up to 52 I/O or 48 LCD segment lines (= 192 segments), individually configurable as I/O or LCD
up to 50 I/O or 46 LCD segment lines (= 184 segments)
Universal port slew rate Stepper motor control modules with high-current ports
SW-selectable 7 modules, 32 dI/dt-controlled ports 4 modules 23 dI/dtcontrolled ports
4
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
Table 1-1: CDC32xxG-C Family Feature List This Device: Item CDC3205GC EMU CDC3207GC MCM Flash CDC3217GC MCM Flash CDC3257GC2 MCM Flash CDC3272GC Mask ROM CDC3231GC Mask ROM 5 modules: PWM0/1, PWM2/3, PWM4/5, PWM6/7, PWM8/9 -
PWM modules, each configurable as two 8-bit PWMs or one 16-bit PWM
6 modules: PWM0/1, PWM2/3, PWM4/5, PWM6/7, PWM8/9 and PWM10/ 11
Pulse/frequency modulator Audio module with auto-decay SW-selectable clock outputs Polling/flash timer output Timers & Counters 16-bit free-running counters with capture/compare modules 16-bit timers 8-bit timers Real-time clock, delivering hours, minutes and seconds Miscellaneous Scalable layout in CAN, RAM and ROM Various HW options selectable at random JTAG interface On-chip debug aids
2: PFM0 and PFM1 2 1 high-current port output operable in power-saving operation modes
CCC0 with 4 CAPCOM CCC1 with 2 CAPCOM 1: T0 4: T1, T2, T3 and T4
CCC0 with 4 CAPCOM
-
set by copy from user program storage during system start-up allows Flash programming Embedded trace module, JTAG JTAG
Core bond-out Supply voltage Case temperature range Package Type Bonded pins
-
3.5 to 5.5 V (limited I/O performance below 4.5 V) 0 C to +70 C - C to +105 C 40
ceramic 257PGA 256
plastic 128QFP 0.5 mm pitch 128 128 128 126 111
ARM and Thumb are the registered trademarks of ARM Limited. ARM7TDMI is the trademark of ARM Limited.
Micronas
May 3, 2005; 6251-609-1DS
5
CDC 3231G-C
1.2. Abbreviations
ADC AM CAN CAPCOM CCC CPU DMA ERM ETM I2C LCD P06COMP PWM SM SPI T UART WAITCOMP Analog-to-Digital Converter Audio Module Controller Area Network Module Capture/Compare Module Capture/Compare Counter Central Processing Unit Direct Memory Access Module EMI Reduction Mode Embedded Trace Module I2C Interface Module Liquid Crystal Display Module P0.6 Alarm Comparator Pulse Width Modulator Module Stepper Motor Control Module Serial Synchronous Peripheral Interface Timer Universal Asynchronous Receiver Transmitter Wait Comparator
DATA SHEET
6
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
1.3. Block Diagram
UVDD UVSS 2.5 V Reg.
VDD VSS Reset/Alarm Test Watchdog Clock PLL/ERM RESETQ TEST TEST2 XTAL1 XTAL2
WAIT WAITH VREFINT VREF AVDD AVSS BVDD 8 PPort0 ARM7TDMI CPU 2.5 V Reg.
RC Oscillator 26-Input Interrupt Controller RTC Power Saving
SRAM 1.5K x 32
JTAG Test and Debug Interface
5
PPort1
PPort2
2
Wait Comp. P06 Comp.
Memory Controller
Bridge
8
32
16/32
ROM 32K x 32 SFR 4K x 16 Patch 10 Locations
UPort0
8
UPort1
8
HPort0
3
Bandgap Ref. UPort2 10-bit ADC Bridge 8 UPort3 7
HPort2
4
UART 0 SPI 0 SPI 1 CAN 0 I C0
2
LCD Control Audio Module Clock Out 0
Stepper Motor Control 8-bit PWM 0 8/16-bit PWM 1 8-bit PWM 2
16-bit Timer 0 8-bit Timer 1 8-bit Timer 2 8-bit Timer 3 8-bit Timer 4
16-bit CCC 0 CAPCOM 0 CAPCOM 1 CAPCOM 2 CAPCOM 3
8
HPort3
4
UPort4
4
UPort5
4
HPort4
Clock Out 1
8/16-bit PWM 3 8-bit PWM 4 8/16-bit PWM 5 8-bit PWM 6 8/16-bit PWM 7
3
4
HPort5
UPort6
2
HPort7
4
UPort7
8-bit PWM 8 8/16-bit PWM 9
4
UPort8
HVDD0 HVSS0 HVDD1 HVSS1
6
Fig. 1-1: CDC3231G-C block diagram
Micronas
May 3, 2005; 6251-609-1DS
7
CDC 3231G-C
DATA SHEET
8
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
2. Packages and Pins
2.1. Package Outline Dimensions
Fig. 2-1: PMQFP128-2: Plastic Metric Quad Flat Package, 128 leads, 14 x 20 x 2.7 mm3 Ordering code: QK Weight approximately 1.78 g
Micronas
May 3, 2005; 6251-609-1DS
9
CDC 3231G-C
2.2. Pin Assignment
DATA SHEET
Pin Functions Not Pin e No. LCD Port Port Basic Mode Special Out Special In Function SEG3.1 CC1-OUT CC1-IN / TMS U3.1 116 SEG3.0 CC2-OUT CC2-IN / TDI U3.0 117 TEST2 118 UVDD 119 UVSS 120 SEG2.6 U2.6 121 SEG2.5 CC1-OUT UART0-RX U2.5 122 SEG2.4 UART0-TX CC1-IN U2.4 123 SEG2.3 CC2-OUT U2.3 124 SEG2.2 CC2-IN U2.2 125 SEG7.7 CO0 U7.7 126 SEG7.6 CO1 U7.6 127 SEG7.5 LCK U7.5 128 SEG7.4 U7.4 1 NC 2 NC 3 NC 4 SEG5.2 U5.2 5 SEG5.1 U5.1 6 SEG5.0 U5.0 7 SEG2.1 SDA0 WP6/SDA0/CAN0U2.1 8 RX SEG2.0 SCL0/CAN0-TX SCL0 U2.0 9 SEG1.7 WP0/PINT0 U1.7 10 SEG1.6 INTRES/CO0 PINT1 U1.6 11 SEG1.5 CO1/CO0Q PINT2 U1.5 12 TEST 13 RESETQ/ALARMQ 14 XTAL2 15 XTAL1 16 VSS 17 VDD 18 SEG1.4 ITSTOUT/AM-OUT U1.4 19 SEG1.3 MTO/AM-PWM WP3 U1.3 20 SEG1.2 INTRES/T0-OUT MTI/ITSTIN U1.2 21 SEG1.1 T1-OUT U1.1 22 SEG1.0 T2-OUT U1.0 23 SEG0.7 T3-OUT WP4 U0.7 24 SEG0.6 CC3-OUT/T4-OUT CC3-IN U0.6 25 SEG0.5 CC3-OUT U0.5 26 SEG0.4 CO1 PINT5 U0.4 27 SEG0.3 PWM0 U0.3 28 SEG0.2 PWM1 U0.2 29 SEG0.1 PWM2 U0.1 30 SEG0.0 PWM3 U0.0 31 PWM4 H7.3 32 PWM6 H7.2 33 PWM8 H7.1 34 PWM9 H7.0 35 NC 36 NC 37 NC 38 NC 39 NC 40 NC 41 SMD1+ SMD-COMP3 H5.3 42 SMD1SMD-COMP2 H5.2 43 HVDD0 44 HVSS0 45 SMD2+ SMD-COMP1 H5.1 46 SMD2SMD-COMP0 H5.0 47 SMA1+ SMA-COMP3 H4.3 48 SMA1SMA-COMP2 H4.2 49 SMA2+ SMA-COMP1 H4.1 50 SMA2SMA-COMP0 H4.0 51
128 1
116
115
103 102
38 39 51 52 64
65
NC = not connected, leave vacant (...) = future usage
Pin Not No. e Basic Function 115 U3.2 114 U3.3 113 U3.4 112 U3.5 111 U3.6 110 U3.7 109 U4.0 108 U4.1 107 U4.2 106 U4.3 105 U8.0 104 U8.1 103 U8.2 102 U8.3 101 U8.4 100 U8.5 99 NC 98 U6.1 97 U6.2 96 P2.0 95 P2.1 94 P0.0 93 P0.1 92 P0.2 91 P0.3 90 P0.4 89 P0.5 88 P0.6 87 P0.7 86 WAITH 85 WAIT 84 BVDD 83 AVSS 82 AVDD 81 VREFINT 80 VREF 79 P1.0 78 P1.1 77 P1.2 76 P1.3 75 P1.4 74 P1.5 73 P1.6 72 P1.7 71 H0.0 70 H0.1 69 H0.2 68 NC 67 NC 66 NC 65 NC 64 NC 63 NC 62 NC 61 H2.0 60 H2.1 59 HVSS1 58 HVDD1 57 H2.2 56 H2.3 55 H3.0 54 H3.1 53 H3.2 52 H3.3
Pin Functions Port Port Special In Special Out CC0-IN / TCK CC0-OUT CO0/TDO SPI0-CLK-IN SPI0-CLK-OUT SPI0-D-IN TO3 SPI0-D-OUT SPI1-CLK-IN SPI1-CLK-OUT SPI1-D-IN CC0-OUT CC0-IN SPI1-D-OUT CAN0-TX CAN0-RX/WP5 TO2
LCD-CLK-IN WP9 LCD-SYNC-IN PINT3/WP8 WP7
LCD-CLK-OUT LCD-SYNC-OUT
LCD Mode SEG3.2 SEG3.3 SEG3.4 SEG3.5 SEG3.6 SEG3.7 BP0 BP1 BP2 BP3 SEG8.0 SEG8.1 SEG8.2 SEG8.3 SEG8.4 SEG8.5 SEG6.1 SEG6.2
P0.6 Comp.
VREF0/WP1 VREF1/WP2 PINT0 PINT1 PINT2 PINT3 PINT5 PWM7 PWM5 PWM3/POL
SMC-COMP0 SMC-COMP1
SMC2SMC2+
SMC-COMP2 SMC-COMP3 SMB-COMP0 SMB-COMP1 SMB-COMP2 SMB-COMP3
SMC1SMC1+ SMB2SMB2+ SMB1SMB1+
Fig. 2-2: Pin Assignment. Please note that in contrast to CDC3205G-C, CDC3207G-C and CDC3272G-C the function CC3OUT is not present on pin 104!
2.3. Pin Function Description
The pin function description differs from the document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS). TEST2 For normal operation with internal code connect TEST2 to System Ground (no internal pull-down).
10
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
2.4. External Components
+5V Supply
100n to 150n
UVDD 5V UVSS VDD
10 Tantal Low ESR 220n Ceramic X7R
HVDD0 to 1
2 x 100n to 150n
+5V Supply System Ground
System Ground
HVSS0 to 1
2.5V
VSS
AVDD
100n to 150n
Analog Supply
XTAL1
18p +5V Supply 4.7k 18p
VREFINT 5V
10n, Ceramic
2.5V XTAL2
AVSS BVDD
150n Ceramic X7R
Analog Ground
Resetq System Ground
47n
RESETQ
Fig. 2-3: CDC3231G-C: Recommended external supply and quartz connection. To provide effective decoupling and to improve EMC behaviour, the small decoupling capacitors must be located as close to the supply pins as possible. The self-inductance of these capacitors and the parasitic inductance and capacitance of the interconnecting traces determine the self-resonant frequency of the decoupling network. Too low a frequency will reduce decoupling effectiveness, will increase RF emissions and may adversely affect device operation. XTAL1 and XTAL2 quartz connections are especially sensitive to capacitive coupling from other pc board signals. It is strongly recommended to place quartz and oscillation capacitors as close to the pins as possible and to shield the XTAL1 and XTAL2 traces from other signals by embedding them in a VSS trace. The RESETQ pin adjacent to XTAL2 should be supplied with a 47nF capacitor, to prevent fast RESETQ transients from being coupled into XTAL2, to prevent XTAL2 from coupling into RESETQ, and to guarantee a time constant of 200s sufficient for proper Wake Reset functionality.
Micronas
May 3, 2005; 6251-609-1DS
11
CDC 3231G-C
DATA SHEET
12
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
3. Electrical Data
3.1. Absolute Maximum Ratings
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum ratings conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. Table 3-1: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins except VSS must be connected to a low-resistive ground plane close to the IC. Symbol VSUP Parameter Main supply voltage Analog supply voltage SM supply voltage Core supply voltage PLL supply voltage Core supply current Main supply current Analog supply current SM supply current @TCASE = 105 C, duty factor = 0.71 1) PLL supply current Vin Input voltage Pin Name UVDD AVDD HVDD0 .. HVDD3 VDD BVDD VDD, VSS, UVDD, UVSS AVDD, AVSS HVDD0 .. HVDD3 HVSS0 .. HVSS3 BVDD U ports, XTAL,RESETQ, TEST, TEST2 P ports VREF H ports Iin Io Input current Output current all inputs U ports, RESETQ, WAITH H ports toshsl Tj Ts Pmax
1)
Min. - 0.3
Max. 6.0
Unit V
VREG ISUP
- 0.3 - 100 - 20 - 250 - 20 UVSS- 0.5
3.0 100 20 250 20 UVDD+0.7
V mA mA mA mA V
UVSS- 0.5 HVSS- 0.5 0 - 5 - 60
AVDD+0.7 HVDD+0.7 2 5 60 indefinite
V V mA mA mA s C C W
Duration of short circuit to UVSS or UVDD, Port SLOW mode enabled Junction temperature under bias Storage temperature Maximum power dissipation
U ports, except in DP mode - 45 - 45
115 125 0.8
This condition represents the worst case load with regard to the intended application.
Micronas
May 3, 2005; 6251-609-1DS
13
CDC 3231G-C
3.2. Recommended Operating Conditions
DATA SHEET
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. Keep UVDD = AVDD during all power-up and power-down sequences. Failure to comply with the above recommendations will result in unpredictable behavior of the device and may result in device destruction. Functional operation of the device beyond those indicated in the "Recommended Operating Conditions" of this specification is not implied, may result in unpredictable behavior of the device and may reduce reliability and lifetime. Table 3-2: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins except VSS must be connected to a low-resistive ground plane close to the IC. Symbol VSUP HVSUP dVDD Parameter Main supply voltage Analog supply voltage SM supply voltage Ripple, peak-to-peak Pin Name UVDD = AVDD HVDDn UVDD AVDD BVDD VDD UVDD AVDD XTAL1 4 4 Min. 3.5 4.75 Typ. 5 5 Max. 5.5 5.25 200 Unit V V mV
dVDD/dt fXTAL fSYS fBUS Vil 1)
Supply voltage up/down ramping rate XTAL clock frequency CPU clock frequency, PLL on Program storage clock frequency, PLL on Automotive low input voltage
20 5
V/s MHz
For a list of available settings see Table 4-1.
U ports H ports P ports U ports, TEST, TEST2 H ports P ports U ports H ports P ports U ports,TEST, TEST2 H ports P ports RESETQ RESETQ 0.86 x xVDD 0.7 x xVDD
0.5 x xVDD 0.3 x xVDD
V
CMOS low input voltage
V
Vih 1)
Automotive high input voltage
V
CMOS high input voltage
V
RVil WRVil
Reset active input voltage Reset active input voltage during power-saving modes and wake reset Reset inactive and alarm active input voltage Reset inactive and alarm inactive input voltage
0.75 0.4
V V
RVim RVih
1)
RESETQ RESETQ
1.5 3.2
2.3
V V
For a list of input types and their supply voltages see Table 2-2 of document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS).
14
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
Table 3-2: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins except VSS must be connected to a low-resistive ground plane close to the IC. Symbol WRVih Parameter Reset inactive input voltage during power-saving modes and wake reset Ext. ADC reference input voltage ADC port input voltage referenced to ext. VREF reference ADC port input voltage referenced to int. VREFINT reference
1)
Pin Name RESETQ
Min. UVDD - 0.4 V 2.56 0 0
Typ.
Max.
Unit V
VREFi PVi
VREF P ports
AVDD VREFi VREFINT
V V
For a list of input types and their supply voltages see Table 2-2 of document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS).
3.3. Characteristics
Listed are only those characteristics that differ from Chapter 3.3 of Document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS). All not differing characteristics, that are not listed here, apply, but in a TCASE temperature range extended to - C to +105 C 40 Table 3-3: UVSS = HVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD < 5.5 V, 4.75 V < HVDDn < 5.25 V, TCASE = - C to +105 C, 40 fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted) Symbol Package Rthjc Rthja Thermal resistance from junction to case Thermal resistance from junction to ambient 10 36 K/W K/W measured on Micronas typical 2-layer board, 1s1p, described in document "Integrated Circuits - Thermal Characterization of Packages" (6200266-1E) (modified JESD-51.3) Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions
Supply Currents (CMOS levels on all inputs, i.e., Vil = xVSS 0.3 V and Vih = xVDD 0.3 V, no loads on outputs) UIDDp UIDDf UIDDs UIDDd UIDDw UVDD PLL mode supply current UVDD FAST mode supply current UVDD SLOW mode supply current UVDD DEEP SLOW mode supply current UVDD WAKE mode supply current UVDD UVDD UVDD UVDD UVDD 0 see
Fig. 3-1
45 70 15 1.24 0.76 50
mA mA mA mA A
fSYS = 24 MHz fSYS = 50 MHz all modules off, 2) all modules off, 2) 3) all modules off, 3) RC and XTAL oscillators off
see
Fig. 3-1
20
1) Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested.
2) 3
Value may be exceeded with unusual hardware option setting
) Measured with external clock. Add typically 120 A for operation on quartz with SR0.XTAL=0 (Oscillator RUN mode).
Micronas
May 3, 2005; 6251-609-1DS
15
CDC 3231G-C
DATA SHEET
Table 3-3: UVSS = HVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD < 5.5 V, 4.75 V < HVDDn < 5.25 V, TCASE = - C to +105 C, 40 fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted) Symbol UIDDst Parameter UVDD STANDBY mode supply current Pin Na. UVDD UVDD UIDDi UVDD IDLE mode supply current UVDD Min. Typ. 1) 35 60 50 see
Fig. 3-1
Max. 75 100 355 380 0.6 2
Unit A A A A mA mA A A
Test Conditions RC oscillator on, XTAL off XTAL oscillator on, RC off 3) RC oscillator on, XTAL off XTAL oscillator on, RC off 3) ADC on, PLL off ADC, buffer and PLL on ADC and PLL off no output activity, SM module off
AIDDa
AVDD active supply current
AVDD
0.35
AIDDq HIDDq
Quiescent supply current
AVDD Sum of all HVDDn
0 0
1 1
10 40
Inputs Ii Input leakage current TEST2 - 1 1 A 0 < Vi < UVDD
1) Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested.
2) 3)
Value may be exceeded with unusual hardware option setting Measured with external clock. Add typically 120 A for operation on quartz with SR0.XTAL=0 (Oscillator RUN mode).
16
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
A 900 800 700 UIDDs (SLOW mode) 600 UIDD 500 400 UIDDd (DEEP SLOW mode) 300 200 100 0 -40 -30 -20 -10 UIDDi (IDLE mode)
0
10
20
30
40
50 TCASE
60
70
80
90
100 110 120 C
Fig. 3-1: Typical UIDD characteristics over temperature @ fXTAL=4MHz, 5V
3.4. Recommended Quartz Crystal Characteristics
See Chapter 3.4 of document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS).
Micronas
May 3, 2005; 6251-609-1DS
17
CDC 3231G-C
DATA SHEET
18
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
4. CPU and Clock System
4.1. Recommended Register Settings
Settings for PMF, IOP and WSR differing from those given in Table 4-1 must not be used and may result in undefined behavior. It is required not to operate I/O faster than ROM. Suppression Strength (SUP) and Clock Tolerance (TOL) may be varied between zero and the values for strong settings according to the rules in Section 4.4.2 of the document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS). The given limits must not be exceeded.
Table 4-1: PLL and ERM modes: Recommended settings and resulting operating frequencies (MHz) fXTAL CPU Flash I/O ERMC.EOM = 1 Weak SUP TOL fSYS 4 16 24 PLLC. PMF 3 5 fBUS 8 8 12 32 7 8 10.67 WSR fIO= f0 8 8 IOC. IOP 1 2 Normal SUP TOL Strong SUP TOL ERMC.EOM = 2 or 3 Weak SUP TOL Normal SUP TOL Strong SUP 22 31 33 31 19 23 37 37 42 14 28 28 30 35 37 TOL 11 12 2 12 9 7 6 6 1 7 8 10 9 8 6
0x11 0x22 0x11 0x33 0x22
0 0 0
8 12 10 12 12
0 0 0 0 0
14 15 10 12 12
0 0 0 0 0
15 15 10 12 12
8 12 12 16 16
4 6 2 8 8
14 21 21 28 19 23 28 35 42 8 17 24 26 35
7 11 2 12 9 7 6 6 1 4 8 12 11 6
8
3
0 0
40 48 5 10 20 30
9 11 1 3 5
10 12 10 10 10
0x33 0x33 0x00 0x11 0x22
8 8 10 10 10
4 5 0 1 2
0 0 0 0 0
6 1 5 10 14
0 0 0 0 0
6 1 8 15 14
0 0 0 0 0
6 1 14 15 14
21 25 5 10 15
6 1 3 5 8
40 50
7 9
10 12.5
0x33 0x33
10 10
3 4
0
6
0
6
0
6
21
6
set ERMC.EOM=0
set ERMC.EOM=0
Micronas
May 3, 2005; 6251-609-1DS
19
CDC 3231G-C
DATA SHEET
20
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
5. Memory and Special Function ROM (SFR) System
address range
(16M) 00FF.FFFF CR.MAP = 00
RESETQ = 1
CR.MAP = 01 CR.MAP = 1x
RESETQ = 0
TEST2-Pin = 0 TEST2-Pin = 1
.5M
F8.0000
I/O
I/O
I/O
F0.0000
.5M rsvd debug
SFR
SFR
SFR
E0.0000
2M
C0.1800
RAM 6KB
C0.0000
RAM 6KB
RAM 6KB
A0.0000
8M
22.0000
ROM 128KB
20.0000
ROM 128KB
2.0000 1800
2M RAM 6KB ROM 128KB SFR ROM 128KB SFR
0
Fig. 5-1: Address Map. Most Common Settings
Micronas
May 3, 2005; 6251-609-1DS
21
CDC 3231G-C
Warning: Since only a 24-bit address space is supported, do not use addresses outside this range when debugging this device.
DATA SHEET
22
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
6. Core Logic
6.1. Control Word (CW)
A number of important system configuration properties are selectable during device start-up by means of a unique Control Word (CW). long as MFPLR.MFPL is 1 (= state after UVDD power-up). Setting it to 0 requires internal SW. By this means, an effective device lock mechanism is implemented, that prevents unauthorized access to internal SW. In ROM parts, flag MFPLR.MFPL is available, but does not lock the Multi Function port. Thus Table 6-1 reduces to Table 6-2. Table 6-2: CW fetch in ROM parts (QFP128) Control Word Fetch desired from Necessary Reset config. of pins TEST2 Internal ROM External via Multi Function port Int. Special Function ROM 0 0 1 TEST 0 1 x
6.1.1. Reset Active
At the end of the reset period, the device fetches this CW from address locations 0x20 to 0x23 of a source that is determined by the state of pins TEST and TEST2 and flag MFPLR.MFPL, see Table 6-1 for MCM parts, Table 6-2 for ROM parts. Table 6-1: CW fetch in MCM parts (QFP128) Control Word Fetch desired from Necessary Reset configuration TEST2 Int. Flash Int. Flash Ext. via Multi Function port Int. Special Function ROM 1 x 0 0 TEST 0 1 MFPL x 1 0 1) x
6.1.2. Reset Inactive
When exiting Reset, the CW is read and stored in the Control Register (CR) and the system will start up according to the configuration defined therein. Normally the CW is fetched from the same memory that the system will start executing code from. Table 6-3 gives fix CWs for a list of the most commonly used configurations.
1) Only available after a non-Power-On RESET with MFPL = 0 set before
As can be seen from Table 6-1, the device disables external access (through the Multi Function port) to internal code, as
Table 6-3: Some common system configurations and the corresponding CW setting Part Type MCM ROM ROM Program Start desired from Additional desired properties Necessary CW 31:16 int. 16-Bit Flash (Am29LV400BT) int. 32-Bit ROM, 16-Bit mode int. 32-Bit ROM, 32-Bit mode Don't care Don't care 0xFFBA 15:0 0x7F5F 0x7F5F 0x775F
Micronas
May 3, 2005; 6251-609-1DS
23
CDC 3231G-C
DATA SHEET
24
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
7. IRQ Interrupt Controller Unit (ICU)
Table 7-1: ICU Input Availability Table 7-1: ICU Input Availability ISN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Interrupt Source Default vector, not connected CC0OR CC1OR PINT0 PINT1 CAN0 SPI0 Timer 1 Timer 0 P06 COMP RESET/ALARM WAIT COMP UART0 PINT2 WAPI CC2OR CC3OR Timer 2 RTC I2C0 Timer 3 SPI1 COMMRX/TX PINT5 PINT3 (Not connected) (Not connected) (Not connected) (Not connected) (Not connected) ISN 30 31 Interrupt Source Timer 4 (Not connected)
Micronas
May 3, 2005; 6251-609-1DS
25
CDC 3231G-C
DATA SHEET
26
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
8. Hardware Options
8.1. Functional Description
Hardware Options are available in several areas to adapt the IC function to the host system requirements. For details see the document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251579-1DS). Hardware Option setting requires two steps: 1. selection is done by programming dedicated address locations in the HW Options field with the desired options' code. 2. activation is done by copying the HW Options field to the corresponding HW Options registers at least once after each reset. In this device, as in EMU and MCM devices, all HW Options are SW progammable. In future mask ROM derivatives the clock options and the Watchdog, Clock and Supply Monitors may be hard wired according to the HW Options field of the ROM code hex file. Those options can only be altered by changing a production mask. To ensure compatible option settings in this IC and future mask ROM derivatives when run with the same ROM code, it is mandatory to always write the HW Options field to the HW option registers directly after reset.
Micronas
May 3, 2005; 6251-609-1DS
27
CDC 3231G-C
DATA SHEET
28
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
9. Register Cross Reference Table
9.1. 8-Bit I/O Region
Table 9-1: Base address 0x00F80000 Offs. 0xFFC 0x200 0x1FC 0x000 Byte Address 3 Remarks 2 1 0 7 CAN reserved CAN 0 Module CAN RAM
Table 9-2: Base address 0x00F81000 Offs. 0x1FC 0x040 0x03C 0x014 0x010 0x00C 0x008 0x004 0x000 Byte Address 3 Remarks 2 1 0 7 CAN reserved CAN0 CTIM TEC BT2 STR Module CAN register
ESM ICR IDM IDX
REC BT3 ESTR
OCR BT1 CTR
Micronas
May 3, 2005; 6251-609-1DS
29
CDC 3231G-C
DATA SHEET
Table 9-3: Base address 0x00F90000 (formerly 1F00) Offs. 0x0FC 0x0F8 0x0F4 0x0F0 0x0EC 0x0B0 0x0AC 0x0A8 0x0A4 0x0A0 0x09C 0x080 0x07C 0x078 0x074 0x070 0x06C 0x068 0x064 0x060 0x05C 0x058 0x054 0x050 0x04C 0x048 0x040 0x03C 0x030 0x02C 0x028 0x024 0x020 0x01C 0x018 0x014 0x010 0x00C 0x008 0x004 0x000 Byte Address 3 TST2 TST5 Remarks 2 TST1 1 TST3 TSTAD3 0 TST4 TSTAD2 Module Test reserved for DIGITBus 64 byte ANAA AD0 UA0IM UA0D 32 byte CCC0H CC3I CC2I CC1I CC0I CCC0L CC3M CC2M CC1M CC0M CAPCOM0 CC3 CC2 CC1 CC0 8 byte Core Logic Stepper Motor Module VDO Timer Timer0 reserved for CAPCOM1 16 byte AMDEC IRPM1 AMF IRPM0 AMAS AMPRE 8 byte reserved for UART1 SPI1M SR1 SR0 SPI1D SPI0M CO0SEL SPI0D Core Logic SPI Core Logic Audio Module Port Interrupt ADC UART0
UA0BR1
UA0IF UA0BR0
AD1 UA0CA UA0C
CC3H CC2H CC1H CC0H
CC3L CC2L CC1L CC0L
SMVMUX SMVSIN TIM4 TIM0H
DBG SMVCMP SMVC TIM3 TIM0L TIM2
CSW1 SMVCOS TIM1
ANAU CSW0
30
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
Table 9-4: Base address 0x00F90100 (formerly 1E00) Offs. 0x0FC 0x0F0 0x0EC 0x0E8 0x0E4 0x0E0 0x0DC 0x0D8 0x0D4 0x0D0 0x0CC 0x0C8 0x0C4 0x0C0 0x0BC 0x060 0x05C 0x058 0x054 0x050 0x04C 0x048 0x044 0x040 0x03C 0x020 0x01C 0x018 0x014 0x010 0x00C 0x008 0x004 0x000 Byte Address 3 Remarks 2 1 0 16 byte UA0 PM Module HW Options
P7P P3P P11P SP2C PF0C C1C RZPC T3C
P7C P3C P11C SP1C AC C0C CO01C T2C
P5P P1P P9P SP0C LC CO1C CO00C T1C
P5C P1C P9C SMC DC DMAC T4C T0C 96 byte reserved for PFM
PWMC PWM7 PWM3 PWM6 PWM2 PWM9 PWM5 PWM1 PWM8 PWM4 PWM0 32 byte reserved for I2C1
PWM
I2C
I2C0 I2CM0 I2CRS0 I2CWD10 I2CRD0 I2CWD00 I2CWP10 I2CWS10 I2CWP00 I2CWS00
Micronas
May 3, 2005; 6251-609-1DS
31
CDC 3231G-C
DATA SHEET
Table 9-5: Base address 0x00F90400 Offs. 0x0FC 0x0F8 0x0F4 0x0F0 0x0EC 0x0E8 0x0E4 0x0E0 0x0DC 0x0D8 0x0D4 0x0D0 0x0CC 0x0C8 0x0C4 0x0C0 0x0BC 0x0B8 0x0B4 0x0B0 0x0AC 0x090 0x084 0x080 0x074 0x070 0x064 0x060 0x054 0x050 0x044 0x040 0x034 0x030 0x024 0x020 0x014 0x010 0x004 0x000 Byte Address 3 HxLVL Remarks 2 HxNS 1 HxTRI 0 HxPIN HxD H-Port7 reserved for HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD H-Port6 H-Port5 H-Port4 H-Port3 H-Port2 reserved for HxPIN HxD P2PIN P1PIN P0PIN H-Port1 H-Port0 P-Ports P2LVL P1LVL P0LVL P2IE P1IE P0IE P-Port 2 P-Port1 P-Port 0 reserved U-Port 8 U-Port 7 U-Port 6 U-Port 5 U-Port 4 U-Port 3 U-Port 2 U-Port 1 U-Port 0 Module H-Ports
HxLVL HxLVL HxLVL HxLVL
HxNS HxNS HxNS HxNS
HxTRI HxTRI HxTRI HxTRI
HxLVL
HxNS
HxTRI
U-Ports
UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM
UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS
UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI
UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD
32
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
Table 9-6: Base address 0x00F90500 Offs. 0x0FC 0x080 0x07C 0x078 0x074 0x070 0x06C 0x068 0x064 0x060 0x05C 0x058 0x054 0x050 0x04C 0x040 0x03C 0x030 0x02C 0x028 0x024 0x020 0x01C 0x014 0x010 0x00C 0x008 0x004 0x000 Byte Address 3 Remarks 2 1 0 128 Bytes SMX POL RTCC OSC WSC WPM8 WPM0 Polling RTC Module reserved Power Saving
Wake Ports mode RTC
WPM6 RTC SSC SSR
WPM4
WPM2
WUS
Wake-up source reserved
GBus Core Logic
WSR IOC ERMC PLLC
Clock, PLL, ERM
reserved ULCDLD
LCD
Patch PER PDR PAR
Micronas
May 3, 2005; 6251-609-1DS
33
CDC 3231G-C
9.2. 32-Bit I/O Region
DATA SHEET
Table 9-7: Base address 0x00FFFD00 Offs. 0x0FC 0x004 0x000 Byte Address 3 Remarks 2 1 0 252 bytes reserved CR Control Register Module Core Logic
Table 9-8: Base address 0x00FFFE00 Offs. 0x0FC 0x000 Byte Address 3 Remarks 2 1 0 Module reserved for DMA
Table 9-9: Base address 0x00FFFF00 Offs. 0x0FC 0x0F4 0x0F0 0x0EC 0x0C8 0x0C4 0x0C0 0x0BC 0x040 0x03C 0x020 0x01C : 0x004 0x000 Byte Address 3 Remarks 2 1 0 12 bytes reserved CRF PRF FIQ registers 40 bytes reserved IRQ registers PEPRIO AFP CRI 128 bytes reserved Interrupt source nodes ISN31 : ISN7 ISN3 ISN30 : ISN6 ISN2 ISN29 : ISN5 ISN1 ISN28 : ISN4 ISN0 Module IRQ and FIQ Interrupt Controller
VTB PESRC
34
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
9.3. Modified Registers
Listed are only those registers that are differing from document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-5791DS).
9.3.1. Standby Registers
(cf. chapter 6.3 in "CDC32xxG-C Automotive Controller Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS))
SR0
7
r/w r/w r/w r/w x TIM2 LCD SM
Standby Register 0
6
I2C0 TIM3 x x
5
x TIM4 PSLW x
4
x x UART0 x
3
x x ADC SPI1
2
x x x CAN0
1
x x TIM1 CCC0
0
x x XTAL SPI0
Offs 3 2 1 0 Res
0x00000100
9.3.2. UVDD Analog Registers
(cf. chapter 6.4.9 in "CDC32xxG-C Automotive Controller Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS))
ANAU
7
r/w EAL 0
Analog UVDD Register
6
x 0
5
LS
4
3
x
2
x
1
x 0
0
VE 0
0
Micronas
May 3, 2005; 6251-609-1DS
35
CDC 3231G-C
DATA SHEET
36
May 3, 2005; 6251-609-1DS
Micronas
DATA SHEET
CDC 3231G-C
10. Differences
This chapter describes differences of this document to predecessor document "CDC3231G-C Automotive Controller" (6251-609-1PD).
Section 1. Introduction 2. Pins 3. Electrical Characteristics Description Table 1-1: devices added Figure 2-3 changed. Characteristics: Changed value: UIDDp, UIDDf, UIDDs, UIDDd, UIDDi, AIDDa 4. CPU and Clock System 5. Memory and Special Function ROM System Table 4-1: entry for fXTAL = 4 MHz, fSYS = 8 MHz deleted Table 4-2: deleted Figure 5-1: Warning added
Micronas
May 3, 2005; 6251-609-1DS
37
CDC 3231G-C
11. Data Sheet History 1. Advance Information: "CDC3231G-C V1.0 Automotive Controller Specification", Jan. 13, 2003, 6251-609-1AI. First release of the advance information. Originally created for HW version CDC3231G-C1. 2. Advance Information: "CDC3231G-C Automotive Controller ", June 30, 2003, 6251-609-2AI. Second release of the advance information. Originally created for HW version CDC3231G-C2. 3. Preliminary Data Sheet: "CDC3231G-C Automotive Controller ", Feb 26, 2004, 6251-609-1PD. First release of the preliminary data sheet. Originally created for HW version CDC3231G-C2. 4. Data Sheet: "CDC3231G-C Automotive Controller ", May 3, 2005, 6251-609-1DS. First release of the data sheet. Originally created for HW version CDC3231G-C2.
DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-609-1DS
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
38
May 3, 2005; 6251-609-1DS
Micronas

▲Up To Search▲

Price & Availability of CDC3231G-C

	To Download CDC3231G-C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .